Without limiting the scope of the invention, its background is described in connection with forming FETs in HgCdTe, as an example.
Heretofore, in this field, it has been known that n+ on p diodes formed in HgCdTe are susceptible to surface leakage effects. There are numerous causes for surface leakage. Two of the more common causes are trapping states in the dielectric of MIS regions adjacent to the diode area, and high electric field densities which form near the corners of the n+ region. These situations lead to tunneling current contributions which increase the reverse bias leakage and reduce the breakdown voltage of HgTeCd diodes. In both of these cases, the leakage is produced in a relatively small area near the semiconductor surface immediately adjacent to the n+/p junction.